Webinar (Asia Timezones) Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis
Circuit Designers, CAD Engineers, Design & CAD Managers
Date / Time / Timezone:
2019-05-08 / 13:00:00 / IST
2019-05-08 / 15:30:00 / CNST
2019-05-08 / 16:30:00 / JST/KST
In this webinar we will discuss current challenges of statistical circuit analysis and show solutions with their pros and cons. Various methods for estimating yield and robustness will be shown (quasi Monte Carlo, most probable points, tail extrapolation, machine learning, corner runs, hierarchical analysis, and more). Efficiency and accuracy will be discussed, as well as their applicability to actual circuit analysis problems. There will be time to answer questions interactively after the webinar.
This free webinar is intended for full-custom circuit designers, project leaders and managers responsible for design verification and full custom design for yield.
Learn methods and tools for analog verification with Monte Carlo, PVT Corners and Worst-Case Analysis