Register for MunEDA 24Mar2017 Webinar on High Sigma Variation Analysis for Memories
Analog and memory circuit designers, design managers, CAD engineers, CAD managers
Date / Time / Timezone:
2017-03-24 / 09:30:00 / PDT/PST
2017-03-24 / 12:30:00 / EDT/EST
2017-03-24 / 13:30:00 / BRT/BRST
2017-03-24 / 16:30:00 / BST/GMT
2017-03-24 / 17:30:00 / CEST/CET
Memories are often designed close to the leading edge of process technology. As a result such designs can suffer performance problems stemming from high variation of device Vth, mobility, and size mismatch. Designers of these leading edge memories must adopt clever methods to account for mismatch sensitivity in order to design robust systems.
We will introduce how MunEDA variation and optimization platform will help you to fully wring out potential yield issues in your memory and custom-digital designs.
• Why is Monte Carlo analysis not enough for high-yield memory verification.
• How can MunEDA high sigma analysis and optimization software be leveraged to achieve high-performance and reliable memory and high-sigma designs?
• What is the math behind MunEDA's sensitivity-based verification technology? -- with enough math/statistics to be interesting but not overwhelming.
• How can MunEDA sensitivity-based tools be useful to test and confirm and validate current intuition of my memory designs.