SRAM parametric yield analysis
IC Design & CAD
Date / Time / Timezone:
2015-09-09 / 10:00:00 / PDT/PST
2015-09-09 / 13:00:00 / EDT/EST
2015-09-09 / 14:00:00 / BRT/BRST
2015-09-09 / 18:00:00 / BST/GMT
2015-09-09 / 19:00:00 / CEST/CET
In this webinar we will discuss current challenges of statistical circuit analysis of SRAM with Monte Carlo techniques and worst-case analysis, and will show solutions with their pros and cons. Efficiency and accuracy will be discussed, as well as their applicability to actual circuit analysis problems. We will address special topics of high-sigma yield analysis and variation analysis of hierarchical, large regular structures.
There will be time to answer questions interactively after the webinar.