Fast and Accurate High-Sigma Analysis with Worst-Case Points
Analog Design/Analog EDA, M. Pronath, MunEDA
Videos
FACTI Centro de Tecnologia da Informação Renato Archer (Brazil) – Semiconductor & EDA in Brazil – The CITAR Project – Radiation Hardness by Design RHBD
Session 8.3, S. Finco, CTI Renato Archer
NCS Nippon Control Systems (Japan) – Japan Semiconductor Industry Review
Session 8.2, K. Tsutsumi, NCS Nippon Control Systems
MunEDA – New WiCkeD feature Cellset for topology change during optimization of RF circuits (BEYOND5)
Session 8.1, M. Sylvester, MunEDA
FACTI Centro de Tecnologia da Informação Renato Archer (Brazil) – Optimization of the control circuit of an LCL Rad Hard using the WiCkeD EDA tool (CITAR Project)
Session 7.4, R. Hassib, CTI Renato Archer
SONIX Technology (Taiwan) – Circuit Verification and Cost (Area) Optimization using MunEDA WiCkeD
Session 7.3, H. J. Chen, SONIX Technology
STMicroelectronics (France, Marseille) – Methodology for Trimmed Circuits Sizing and PVT Optimization
Session 7.2, O. Lauzier, STMicroelectronics
Fraunhofer ENAS ASE – Innovative Systems and Automated Design for 5G/6G Connectivity and Radar Applications (INNOSTAR)
Session 7.1, J. Temme, Fraunhofer ENAS ASE
MunEDA Tutorial – LVF Standard Cell Characterization Flow with WiCkeD
Session 6.4, V. Glöckel, MunEDA
Infineon Technologies – Standard Cell Characterization with LVF Liberty Variation Format and High-Sigma Methods for ULP Ultra Low Power
Session 6.2, K. Narayanan, Infineon Technologies
Reutlingen University – Research and Education in the Electronics & Drives Lab – Procedural Automation Solutions for Analog IC Design (HoloDeC)
Session 6.1, J. Scheible, Reutlingen University
Infineon Technologies (Italy) – Using WiCkeD Gangway in Infineon Analog Generator Projects
Session 5.4, D. Demiri, Infineon Technologies
Fraunhofer IIA EAS (Dresden) – Linking WiCkeD and Intelligent IP Layout Generators for Fast Analog IC Design and IP Reuse (AnastASICA)
Session 5.3, B. Prautsch, Fraunhofer IIA EAS
