Lantiq – Process Characterization in 40nm and Level Shifter Optimization in 65nm (RF Design)
Session 3.1, G. Golla, Lantiq
MunEDA User Group Meeting
STMicroelectronics Crolles – WiCkeD/Virtuoso Design Intents Flow for STMicroelectronics CMOS14FDSOI (14nm)
Session 2.3, R. Stewart, STMicroelectronics
Altera – Power and performance optimization with transistor variables on custom circuits using MunEDA WiCkeD
Session 2.2, G. H. Oh, Altera
Berkeley Design Automation – Nanometer Circuit Verification & Analog Characterization Environment
Session 1.4, P. Estrada, Berkeley Design Automation
Verification and Optimization of Digital Radio Receiver Sub Circuits
Session 7.1, A. Bänisch, University Erlangen
Sizing of standard cells in worst-case process conditions in 110nm BCD9s
Session 6.2, F. Adduci, STMicroelectronics
MunEDA Tutorial – SRAM & Memory Design- high-sigma yield analysis and optimization with WiCkeD
Session 5.1, C. Roma, MunEDA
