HLMC – 55nm to 40nm Bandgap porting with SPT & High gain Amp optimization with MunEDA WiCkeD
Session 5.2, L. Ye, HLMC
MunEDA User Group Meeting
Infineon – Safeguarding Holdtime Margin for Internal Scan Chain in Multibit-Register Standardcells
Session 4.2, A. Lang, Infineon
Sapienza University Rome – Digital standard cell noise margin optimization, also considering aging effects with MunEDA WiCkeD and Synopsys MOSRA tools (MANON)
Session 4.1, Z. Abbas, Sapienza University Rome
STMicroelectronics – IOs circuit optimization activities to enhance productivity, circuit robustness and improve existing reliability flow
Session 3.4, A. Aggarwal, STMicroelectronics
Infineon – Reliability Aware Design of Relaxation Oscillator in Advanced CMOS Technology Nodes with WiCkeD
Session 3.3, W. Wang, Infineon
STMicroelectronics – I/O Design Optimization Flow for Reliability In Advanced CMOS Nodes
Session 3.2, V. Huard, STMicroelectronics
MunEDA – Reliability & Robustness Based Design Using WiCkeD (Presentation & Tool-Demo)
Session 3.1, C. Roma, STMicroelectronics
Novatek – S&H Sample & Hold (ADC) Mismatch Analysis and Sizing using WiCkeD
Session 2.4, J. Chu, Novatek
Lantiq – Sign-off flow for RF design with WiCkeD in a 65nm Technology
Session 2.3, D. Diaz-Lopez, Lantiq
SMIC – Process related yield debug and optimization of analog IP with MunEDA WiCKeD
Session 2.2, C. Zhu, SMIC
