Verification and Optimization of Digital Radio Receiver Sub Circuits
Session 7.1, A. Bänisch, University Erlangen
MUGM 2012
Sizing of standard cells in worst-case process conditions in 110nm BCD9s
Session 6.2, F. Adduci, STMicroelectronics
MunEDA Tutorial – SRAM & Memory Design- high-sigma yield analysis and optimization with WiCkeD
Session 5.1, C. Roma, MunEDA
Introduction Evatronix IP Cores and Services & Low/Fast Speed Differential OpAmp in 40nm TSMC with WiCkeD
Session 3.2, C. Elgert, Evatronix
Sizing of FPGA cells with combination of WiCkeD and Least Squares Fitting
Session 2.4, J. Lin, Altera
WiCkeD + CustomSim-XA for Fast Monte Carlo & WiCkeD + Cadence for Design Intent Capturing
Session 2.3, E. Raciti, STMicroelectronics
Low Power MPSoC Circuit Design in GLOBALFOUNDRIES 28nm CMOS with WiCkeD
Session 1.5, S. Höppner, Technical University Dresden