Many thanks for your past interest in our EDA tools and solutions for automated circuit migration, verification, sizing, and optimization… Read More »Webinar Invite: Fast and Accurate High-Sigma Analysis with Worst-Case Points on November 14th
The blog highlights a presentation by Peter Huber of Infineon at MunEDA’s user group meeting, focusing on SRAM design optimization challenges.
The Brazilian Ministry of Science and Technology’s Renato Archer Information Technology Center (CTI) presented research on designing Latching Current Limiter (LCL) circuits for space applications with radiation-hardened techniques.
The MunEDA User Group Meeting highlighted ST Microelectronics’ success with MunEDA’s WiCkeD tool for analog circuit optimization.
Russell Mohn, Co-Founder at InPlay Inc., uses MunEDA’s WiCkeD and SPT tools for RF/AMS chip design. InPlay focuses on wireless connectivity and RFID smart sensors.
Many thanks for your past interest in our EDA tools and solutions for automated circuit migration, verification, sizing, and optimization… Read More »Webinar Invite: Enhance Productivity with Machine Learning in the Analog Front-End Design Flow on April 11th
Many thanks for your past interest in our EDA tools and solutions for automated circuit migration, verification, sizing, and optimization… Read More »Webinar Invite: Post-layout Circuit Sizing Automation on October 4th
The author discusses advancements in automated layout generation for analog integrated circuits (ICs), focusing on ADC design.
Many thanks for your past interest in our EDA tools and solutions for automated circuit migration, verification, sizing, and optimization… Read More »Webinar Invite: Simulate Trimming for Circuit Quality of Smart IC Design on April 6th
Many thanks for your past interest in our EDA tools and solutions for automated circuit migration, verification, sizing, and optimization… Read More »Webinar Invite: Optimal circuit sizing strategies for performance, low power, and high yield of analog and full-custom IP
The blog discusses the complexities of analog circuit design and introduces MunEDA’s webinar on optimal circuit sizing.
My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area.
It has been my pleasure to interview Harald Neubauer, CEO of MunEDA. A veteran of the EDA industry, Harald cofounded MunEDA in 2001.
The blog covers MunEDA’s tutorial at the 56th DAC in Las Vegas on Analog IP migration and optimization.
Lurking inside of every Mosfet is a parasitic bipolar junction transistor (BJT). Of course, in normal circuit operation the BJT does not play a role in the device operation.