Publications & Technical Papers


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May
31st
2017
DAC 2017 MunEDA Booth Info Flyer
MunEDA
DAC 2017 MunEDA Booth Info Flyer, May 2017, Austin TX, USA
Sep
30th
2016
MunEDA White Paper - High sigma parametric yield estimation for SRAM and Standard Cells
Dr. Michael Pronath, Dr. Frank Schenkel, MunEDA
Abstract: Verification of SRAM and standard cells poses a specific challenge to the designer because the parametric yield estimation is to be estimated for very low failure rates below 1ppb (10–9), equivalent to >6 Sigma robustness. The simulation effort for standard crude Monte Carlo simulation is not feasible for such low failure rates. This paper compares various approaches to solve the problem with respect to their Efficiency and robustness. The particular failure metrics of SRAM are considered in detail, while the applied methods for high sigma analysis are valid for standard cells as well

September 2016, Munich, Germany
Aug
03rd
2016
Yield-driven Power-Delay-Optimal CMOS full-adder design PVT NBTI (Sapienza, MunEDA)
Authors: Abbas Z, Olivieri M. (Sapienza University Rome), Andreas Ripp (MunEDA)
Abstract: Presentation about detailed results of mathematical optimization algorithm applications to transistor sizing in a full-adder cell design, to obtain the Maximum expected fabrication yield. Including: all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. Transistor sizing verified by Monte Carlo SPICE analysis.

August 2016, Rome, Italy
Mar
31st
2016
IRPS 2016 - BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization - (STMicroelectronics-MunEDA)
F. Cacho, A. Cros, Y. Federspiel, V. Huard (STMicroelectronics), C. Roma (MunEDA)
Reliability Physics Symposium (IRPS), 2016 IEEE International, March 2016, Monterey, USA
Aug
31st
2015
New Technology Migration Methodology for Analog IC Design (using MunEDA SPT Schematic Porting Tool)
Helga Dornelas, Alonso Schmidt (NSCAD), Eric Fabris (UFRGS), Gunter Strube (MunEDA)
SBCCI 2015, August 2015, Salvador, Brazil
Jul
31st
2015
Optimal NBTI Degradation and PVT Variation Resistant Device Sizing in a Full Adder Cell
Zia Abbas, Mauro Olivieri (Sapienza University Rome), Gunter Strube, Andreas Ripp (MunEDA)
ICRITO 2015, July 2015, Noida, India
Aug
31st
2014
Self-biased CMOS current reference based on the ZTC operation condition (using WiCkeD)
P Toledo, D. Cordova, E. Fabris (NSCAD), H. Klimach, S. Bampi (PGMICRO-UFRGS)
SBCCI 2014, August 2014, Porto Alegre, Brazil
May
31st
2014
I/O Design Optimization Flow for Reliability in Advanced CMOS Nodes with WiCkeD
F. Cacho, A. Gupta, A. Aggarwal, G. Madan, N. Bansal, M. Rizvi, V. Huard, P. Garg, C. Arnaud, R. Delater, STMicroelectronics
C. Roma, A. Ripp, MunEDA

IRPS 2014, May 2014, Hawaii, USA
Mar
31st
2014
Atmel-MunEDA Efficient Regression for Robustness Verification with WiCkeD
S. Kern, Atmel Automotive
M. Yakupov, G. Strube, MunEDA

DASS 2014, March 2014, Dresden, Germany
Feb
28th
2014
ZMDI-MunEDA Robustness Verification - Sign-off Regression Flow - DATE 2014
S. Getzlaff, ZMDI
G. Strube, MunEDA

DATE 2014, February 2014, Dresden, Germany
Dec
31st
2012
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) in 65nm
Zia Abbas, Mauro Olivieri, Marat Yakupov, Andreas Ripp
Elsevier Journal of Microelectronics, December 2012, Rome, Italy
Aug
31st
2012
Porting an LDO architecture from 0.18 μm to 0.13 μm technology
DFchip - MunEDA
SBCCI 2012 Brazil, August 2012, João Pessoa, Brazil
Aug
31st
2012
IP Porting Services
DFchip
SBCCI 2012 Brazil, August 2012, João Pessoa, Brazil
Aug
31st
2012
Leading Edge Technology for Brazil‘s IC design Eco-System
NSCAD
SBCCI 2012 Brazil, August 2012, João Pessoa, Brazil
Aug
31st
2012
Yield optimization for low power current controlled current conveyor
Z. Abbas, M. Olivieri, Sapienza University of Rome, Italy
A. Ripp, G. Strube, M. Yakupov, MunEDA GmbH, Munich, Germany

SBCCI 2012, August 2012, Brasília, Brazil
Dec
31st
2011
Process Variations and Probabilistic Integrated Circuit Design
M. Dietrich, J. Haase, Fraunhofer, Dresden, Germany
M. Pronath, MunEDA GmbH, Munich, Germany

December 2011, Munich, Germany
May
31st
2011
Conversion and Optimization Flow for Analog IP Porting
ZMDI - MunEDA
DAC2011, May 2011, San Diego, USA
Feb
28th
2011
Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
Melexis - IMMS - TU Dresden - TU Ilmenau - MunEDA [Link]
V. Boos, J. Nowak, S. Henker, S. Hoeppner, M. Sylvester, H. Grimm

DATE 2011 - Design Automation and Test in Europe Conference, February 2011, Grenoble, France
Aug
31st
2010
Systematic Analysis & Optimization of Analog/Mixed-Signal Circuits Balancing Accuracy and Design Time
STMicroelectronics - MunEDA
Antonio Colaci, Gianluigi Boarin, Andrea Roggero, Lorenzo Civardi, Carlo Roma, Gunter Strube, Andreas Ripp and Michael Pronath

SBCCI 2010 - 23rd Symposium on Integrated Circuit and Systems Design, August 2010, Sao Paulo, Brazil
Feb
28th
2010
Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate
H. Gräb, Xin Pan, Technical University Munich, Germany
ISQED 2010, February 2010, San Jose, CA, USA
Nov
30th
2009
Analog IP Porting by Topology Conversion and Optimization
U. Sobe, A. Graupner, E. Böhme ZMD AG, Dresden, Germany
A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany

IP - ESC 2009, November 2009, Grenoble, France
Apr
30th
2009
Robust Analog Design for Automotive Applications by Design Centering With Safe Operating Areas
U. Sobe, K.-H. Rooch, D. Mörtl, A. Graupner, ZMD AG, Dresden, Germany
A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany

April 2009, Semiconductor Manufacturing, IEEE Transactions on
Mar
31st
2009
Digital Design at a Crossroads
U. Schlichtmann, M. Schmidt, Technical University Munich, Germany
M. Pronath, V. Glöckel, MunEDA GmbH, Munich, Germany
H. Kinzelbach, Infineon Technologies AG, Munich, Germany
M. Dietrich, U. Eichler, J. Haase, Fraunhofer IIS/EAS Dresden, Germany

DATE09, March 2009, Nice, France
Oct
31st
2008
HONEY – Highly Optimized Design Methods for Yield and Reliability 2A713
STMicroelectronics - Infineon - X-FAB - MunEDA - IMMS
EUROPEAN NANOELECTRONICS Forum 2008, October 2008, Paris, France
Aug
31st
2008
Verification of Safe Operating Area (SOA) Constraints in Analog Circuits
X-FAB - ZMD - MunEDA
ZuE 2008 - Reliability and Design, August 2008, Ingolstadt, Germany
Aug
31st
2008
Verification of Safe Operating Area (SOA) Constraints in Analog Circuits
U. Sobe, K.-H. Rooch, D. Mörtl, A. Graupner, ZMD AG, Dresden, Germany
A. Lerch, X-Fab Semiconductor Foundries AG, Erfurt, Germany
M. Pronath, MunEDA GmbH, Munich, Germany

ZuE 2008 - Reliability and Design, August 2008, Ingolstadt, Germany
Apr
30th
2008
Technology Setup for WiCkeD in X-FAB CMOS and BiCMOS Processes for Automotive and Sensor Applications
X-FAB - IMMS - MunEDA
edaWorkshop 2008, April 2008, Hannover, Germany
Apr
30th
2008
Analysis and Optimization of a CMOS Mixer Circuit with WiCkeD
Fraunhofer - MunEDA
edaWorkshop 2008, April 2008, Hannover, Germany
Feb
29th
2008
VeronA - Verification of Analog Circuits - BMBF Project 01 M 3079 edacentrum
Atmel, Bosch, Cadence, Infineon, MunEDA, Qimonda
DATE08, February 2008, Munich, Germany
Feb
29th
2008
Robust Analog Design for Automotive Aplications by Design Centering with Safe Operating Areas
K.-H. Rooch, U. Sobe, ZMD AG, Dresden, Germany
A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany

ISQED´08, February 2008, San Jose, CA, USA
Oct
31st
2007
HONEY – Highly Optimized Design Methods for Yield and Reliability
STMicroelectronics - Infineon - X-FAB - MunEDA - IMMS
MEDEA+ Annual Forum 2007, October 2007, Budapest, Hungary
May
31st
2007
An IP Porting System for Analog Libraries
Faraday Technology Corporation
May 2007, Hsin-Chu/Munich, Taiwan/Germany
May
31st
2007
65nm Technology Based Modelling and Analysis Methodologies based on Variations
Infineon - Fraunhofer - MunEDA - Sigma65
May 2007, Hannover, Germany
Apr
30th
2007
Challenges of reliability oriented design strategies for analog and mixed-signal circuits
A. Ripp, MunEDA GmbH, Munich, Germany
MEDEA-DAC 2007, April 2007, Grenoble, France
Apr
30th
2007
Graph Theoretical Approach for Initial Sizing of Analog Circuits
V. Boos, IMMS GmbH, Erfurt, Germany
DASS 2007, April 2007, Dresden, Germany
Mar
31st
2007
Analog Design Centering and Sizing
H. Gräb, Technical University Munich, Germany
March 2007, Munich, Germany
Feb
28th
2007
Design Tutorial DfY-DfM - Design for Yield and Manufacturability
A. Ripp, MunEDA GmbH, Munich, Germany (Chair)
R. Sommer, IMMS - TU Ilmenau
M. Pronath, MunEDA GmbH, Munich, Germany

ZuD 2007 - Reliability and Design, February 2007, Munich, Germany
Feb
28th
2007
Robust Analog Design for Automotive Applications by Design Centering
K.-H. Rooch, U. Sobe, ZMD AG, Dresden, Germany
M. Pronath, MunEDA GmbH, Munich, Germany

ZuD 2007 - Reliability and Design, February 2007, Munich, Germany
Aug
31st
2006
Yield Optimisation of Power-On Reset Cells and Functional Verification - Power-on Reset Cell (POR) in 350nm CMOS Technology
O. Eisenberger, G. Rappitsch, austriamicrosystems AG, Unterpremstaetten, Austria
B. Obermeier, A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany

ANALOG06, August 2006, Dresden, Germany
Aug
31st
2006
Experimental Verification of Simulation Based Yield Optimization for Power-On Reset Cells
G. Rappitsch, O. Eisenberger, austriamicrosystems AG, Unterpremstaetten, Austria
B. Obermeier, A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany

CICC 2006, August 2006, San Jose, CA, USA
Aug
31st
2006
Circuit Design-for-Yield (DFY) for a 110dB Op-Amp for Automotive and Sensor Applications - Circuit Reference Case: Fully differential folded cascode OTA in 600nm CMOS Technology
K.-H. Rooch, U. Sobe, ZMD AG, Dresden, Germany
M. Pronath, MunEDA GmbH, Munich, Germany

ANALOG06, August 2006, Dresden, Germany
Aug
31st
2006
Modelling of the parametric yield in decananometer SRAM-Arrays - Sense-Amplifier for SRAM-Memory in 90nm and 65nm CMOS Technology
T. Fischer, T. Nirschl, D. Schmitt-Landsiedel, B. Lemaitre, Infineon Technologies, Munich, Germany
Advances in Radio Science 2006, August 2006, Katlenburg-Lindau, Germany
Aug
31st
2006
6T for Embedded SRAM - six sigma design with WiCkeD
T. Fischer, Infineon Technologies AG, Munich, Germany
MUGM 2006, August 2006, Munich, Germany
Jun
30th
2006
Analysis and Optimization of Mismatch in Analog Designs with WiCkeD
STMicroelectronics
June 2006, Agrate, Italy
Jun
30th
2006
Apr
30th
2006
Design for Yield Concepts for Analogue and Mixed-Signal Circuits
M. Pronath, MunEDA GmbH, Munich, Germany
MEDEA-DAC 2006, April 2006, Prien, Germany
Apr
30th
2006
ANASTASIA+ - Successful bridge from basic methodology research to industrial design tool delivery
A. Ripp, MunEDA GmbH, Munich, Germany
MEDEA-DAC 2006, April 2006, Prien, Germany
Feb
28th
2006
DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design
A. Ripp, MunEDA GmbH, Munich, Germany (Chair)
M. Bühler, J. Koehl, IBM Deutschland Entwicklung GmbH, Böblingen, Germany
J. Bickford, J. Hibbeler, IBM Inc., Burlington, USA
U. Schlichtmann, Technical University Munich, Germany
R. Sommer, Infineon Technologies AG, Munich, Germany
M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany

DATE06, February 2006, Munich, Germany
Sep
30th
2005
Robustness and Reliability - Facing new Quality Levels for Automotive ICs with Design for Yield
A. Ripp, MunEDA GmbH, Munich, Germany
EuroDesignCon 2005, September 2005, Munich, Germany
Aug
31st
2005
Fast Automatic Sizing of a Charge-Pump Phase-Locked Loop based on behavioral Models
Infineon Technologies
BMAS 05, August 2005, San Jose, CA, USA
Aug
31st
2005
Advanced Mathematical and Computational Methods fort he Design Centering of Electronic Circuits
M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany
SCEE Summer School 2005, August 2005, Capo D'Orlando, Sicily, Italy
Apr
30th
2005
Seamless Analog/Mixed-Signal Top-Down Design Flow - Applications from Circuit Sizing, Design Centering, and Symbolic Circuit Analysis
R. Sommer, Infineon Technologies AG, Munich, Germany
M. Pronath, MunEDA GmbH, Munich, Germany

MEDEA-DAC 2005, April 2005, Château des Mesnuls, France
Feb
28th
2005
Dec
31st
2004
Linear Regulators for High Temperature Applications
IMMS
EUROSOI 05, December 2004, Granada, Spain
Oct
31st
2004
Systematic Analog/Mixed-Signal Design - Yield Optimization of Analog Circuits with WiCkeD
Bosch - Infineon
MEDEA+ Forum 2004, October 2004, Paris, France
Oct
31st
2004
Systematic Analog/Mixed-Signal Design - Yield Optimization of Analog Circuits with WiCkeD
U. Schlichtmann, H. Gräb, Technical University Munich, Germany
R. Sommer, E. Hennig, Infineon Technologies AG, Munich, Germany
F. Schenkel, MunEDA GmbH, Munich, Germany
T. Ifstroem, Robert Bosch GmbH, Reutlingen, Germany

MEDEA+ Forum 2004, October 2004, Paris, France
Apr
30th
2004
Systematic Analog/Mixed-Signal Design and Design Accuracy
Infineon - MunEDA - TUM
Ekompass Workshop, April 2004, Hannover, Germany
Apr
30th
2004
Systematischer Analog/Mixed-Signal-Entwurf und Designsicherheit
U. Schlichtmann, G. Stehr, T. Massier, H. Gräb, Technical University Munich, Germany
R. Sommer, E. Hennig, Infineon Technoologies AG, Munich, Germany
F. Schenkel, A. Ripp, MunEDA GmbH, Munich, Germany

EKOMPASS04, April 2004, Hannover, Germany
Jan
31st
2004
Industrial Design Tutorial - DFY/DFM - Design for Yield and Manufacturability
Infineon - MunEDA - MEDEA - ANASTASIA
DATE04, January 2004, Paris, France
Jan
31st
2004
Design Tutorial DFY/DFM - Design for Yield and Manufacturability
A. Ripp, MunEDA GmbH, Munich, Germany (Chair)
R. Sommer, E. Hennig, Infineon Technologies AG, Munich, Germany
M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany

DATE04, January 2004, Paris, France
Dec
31st
2003
Design Efficiency and Yield Improvement in Analog Design with WiCkeD
IMMS - Melexis - X-FAB - Infineon - Cadence - MunEDA
Workshop Design Centering 2004, December 2003, Erfurt, Germany
Oct
31st
2003
Initial Sizing of Analog Integrated Circuits by Centering within Topology-Given Implicit Specifications
G. Stehr, M. Pronath, F. Schenkel, H. Gräb, K. Antreich, Technical University Munich, Germany
M. Pronath, F. Schenkel, Munich, Germany
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1257655

ICCAD 2003, October 2003, San Jose, CA, USA
Aug
31st
2003
Tutorial Design for Manufacturability: Statistical Analysis and Yield Optimization of analog integrated circuits
A. Ripp, MunEDA GmbH, Munich, Germany (Chair)
R. Sommer, E. Hennig, Infineon Technologies AG, Munich, Germany
F. Schenkel, M. Pronath, A. Ripp, MunEDA GmbH, Munich, Germany

ANALOG03, August 2003, Heilbronn, Germany
Aug
31st
2003
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing
J. Fischer, E. Amirante, D. Schmitt-Landsiedel, Technical University Munich, Germany
F. Randazzo, G. Iannaccone, Universita degli Studi di Pisa, Italy

August 2003, Munich, Germany
Feb
28th
2003
Design for Manufacturablity
Infineon - MunEDA
DATE03, February 2003, Munich, Germany
Sep
30th
2002
Top-Down Design Methods for Mixed-Signal Applications
Infineon Technologies
MEDEA+ DAC 2002, September 2002, Stresa Lago Maggiore, Italy
Jun
30th
2002
Mixed Signal - Design for Systems on Chip with WiCkeD
Infineon Technologies
June 2002, Munich, Germany
Apr
30th
2002
Dimensionierung analoger integrierter Schaltungen mittels adaptiver Worst-Case-Parametersätze
R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany
GMM/ITG Diskussionssitzung Entwurf von Analogschaltungen 2002, April 2002, Bremen, Germany
Apr
30th
2002
Simulation und Testentwurf für Floating-Gate Defekte (FGD) in analogen integrierten Schaltungen
M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
GMM/ITG Diskussionssitzung Entwurf von Analogschaltungen 2002, April 2002, Bremen, Germany
Apr
30th
2002
Design of Optimal Implicit Tests for Parametric Faults considering Errors of Test Stimuli and Measurements
M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
European Test Workshop 2002, April 2002, Korfu, Greece
Feb
28th
2002
Der Einfluss von Ungenauigkeiten im Teststimulus auf den Test analoger Schaltungen
M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
ITG/GI-Workshop 2002, February 2002, Bad Herrenalb, Germany
Jan
31st
2002
Analog Circuit Sizing using Adaptive Worst-Case Parameter Sets
R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany
DATE02, January 2002, Paris, France
Jan
31st
2002
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
DATE02, January 2002, Paris, France
Jan
31st
2002
WiCkeD 3: Design Centering and Mismatch Analysis for Analog Integrated Circuits
F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany
DATE02, January 2002, Paris, France
Jan
31st
2002
Analog Circuit Synthesis Based on an Iterative Relaxed Worst-Case Formulation
R. Schwencker, F. Schenkel, M. Pronath, H. Gräb, Technical University Munich, Germany
DATE 2002, January 2002, Munich, Germany
Oct
31st
2001
On Parametric Test Design for Analog Integrated Circuits considering Error in Measurement and Stimulus
M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
Modeling, Simulation and Optimization of Integrated Circuits 2001, October 2001, Oberwolfach, Germany
Oct
31st
2001
The sizing rules method for analog integrated circuit design
S. Zizala, J. Eckmüller, Infineon Technologies, Munich
K. Antreich, H. Gräb, Technical University of Munich

ICCAD 2001, October 2001, San Jose, CA, USA
May
31st
2001
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search
F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Gräb, K. Antreich, Technical University Munich, Germany
DAC 2001, May 2001, Las Vegas, NV, USA
May
31st
2001
Estimation of the Influence of Test Stimulus Precision on Test Quality for Parametric Faults in Analog Integrated Circuits
M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
IEEE Mixed Signal Test Workshop 2001, May 2001, Atlanta, GA, USA
Apr
30th
2001
A Fast Method for Identifying Matching-Relevant Transistor Pairs
F. Schenkel, M. Pronath, H. Gräb, K. Antreich, Technical University Munich, Germany
CICC 2001, April 2001, San Diego, CA,USA
Jan
31st
2001
Deterministischer parametrischer Testentwurf für analoge integrierte Schaltungen mit Testbeobachtungen unter Anwendung von Ergebnissen aus dem Toleranzentwurf
V. Glöckel, M. Pronath, H. Gräb, Technical University Munich, Germany
ITG/GI-Workshop 2001, January 2001, Miesbach, Germany
Oct
31st
2000
WiCkeD: Analyse und Dimensionierung analoger Schaltungen unter Berücksichtigung von Mismatch
K. Antreich, J. Eckmüller, H. Gräb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala, Technical University Munich, Germany
ITG/GI-Workshop 2000, October 2000, Darmstadt, Germany
Oct
31st
2000
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits
M. Pronath, V. Gloeckel, H. Gräb, Technical University Munich, Germany
ICCAD 2000, October 2000, San Jose, CA, USA
Apr
30th
2000
WiCkeD: Analog circuit synthesis incorporating mismatch
K. Antreich, J. Eckmüller, H. Gräb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala, Technical University Munich, Germany
CICC 2000, April 2000, Orlando, FL, USA
Feb
29th
2000
The Generalized Boundary Curve - A Common Method for Automatic Nominal
R. Schwencker, F. Schenkel, H. Gräb, K. Antreich, Technical University Munich, Germany
DATE 2000, February 2000, Paris, France
Dec
31st
1999
Testentwurf für analoge Komponenten gemischt analog-digitaler Schaltungen basierend auf der Auswertung des Übertragungsverhaltens
M. Pronath, Technical University Munich, Germany
AES 2000, December 1999, Karlsruhe, Germany
Feb
28th
1999
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints
R. Schwencker, J. Eckmüller, H. Gräb, K. Antreich, Technical University Munich, Germany
DATE 1999, February 1999, Munich, Germany
Jan
31st
1999
Effiziente Modellierung integrierter analoger CMOS-Schaltungen durch Berücksichtigung von Struktureigenschaften
S. Zizala, J. Eckmüller, H. Gräb, K. Antreich, Technical University Munich, Germany
ANALOG99, January 1999, Munich, Germany
Sep
30th
1996
Diagnose für integrierte Analogschaltungen
J. Eckmüller, G. Strube, H. Gräb, Technical University Munich, Germany
ANALOG96, September 1996, Berlin, Germany
Dec
31st
1993
Circuit Analysis and Optimization Driven by Worst-Case Distances
K. Antreich, H. Gräb, C. Wieser, Technical University Munich, Germany
IEEE Transactions CAD, December 1993, ,
Oct
31st
1991
Circuit Optimization Driven by Worst-Case Distances
K. Antreich, H. Gräb, Technical University Munich, Germany
ICCAD 1991, October 1991, Santa Clara, CA, USA