Publications & Technical Papers


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Sep
30th
2016
MunEDA White Paper - High sigma parametric yield estimation for SRAM and Standard Cells
Dr. Michael Pronath, Dr. Frank Schenkel, MunEDA
Abstract: Verification of SRAM and standard cells poses a specific challenge to the designer because the parametric yield estimation is to be estimated for very low failure rates below 1ppb (10–9), equivalent to >6 Sigma robustness. The simulation effort for standard crude Monte Carlo simulation is not feasible for such low failure rates. This paper compares various approaches to solve the problem with respect to their Efficiency and robustness. The particular failure metrics of SRAM are considered in detail, while the applied methods for high sigma analysis are valid for standard cells as well

September 2016, Munich, Germany
Aug
03rd
2016
Yield-driven Power-Delay-Optimal CMOS full-adder design PVT NBTI (Sapienza, MunEDA)
Authors: Abbas Z, Olivieri M. (Sapienza University Rome), Andreas Ripp (MunEDA)
Abstract: Presentation about detailed results of mathematical optimization algorithm applications to transistor sizing in a full-adder cell design, to obtain the Maximum expected fabrication yield. Including: all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. Transistor sizing verified by Monte Carlo SPICE analysis.

August 2016, Rome, Italy
Mar
31st
2016
IRPS 2016 - BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization - (STMicroelectronics-MunEDA)
F. Cacho, A. Cros, Y. Federspiel, V. Huard (STMicroelectronics), C. Roma (MunEDA)
Reliability Physics Symposium (IRPS), 2016 IEEE International, March 2016, Monterey, USA
Aug
31st
2015
New Technology Migration Methodology for Analog IC Design (using MunEDA SPT Schematic Porting Tool)
Helga Dornelas, Alonso Schmidt (NSCAD), Eric Fabris (UFRGS), Gunter Strube (MunEDA)
SBCCI 2015, August 2015, Salvador, Brazil
Jul
31st
2015
Optimal NBTI Degradation and PVT Variation Resistant Device Sizing in a Full Adder Cell
Zia Abbas, Mauro Olivieri (Sapienza University Rome), Gunter Strube, Andreas Ripp (MunEDA)
ICRITO 2015, July 2015, Noida, India
Aug
31st
2014
Self-biased CMOS current reference based on the ZTC operation condition (using WiCkeD)
P Toledo, D. Cordova, E. Fabris (NSCAD), H. Klimach, S. Bampi (PGMICRO-UFRGS)
SBCCI 2014, August 2014, Porto Alegre, Brazil
May
31st
2014
I/O Design Optimization Flow for Reliability in Advanced CMOS Nodes with WiCkeD
F. Cacho, A. Gupta, A. Aggarwal, G. Madan, N. Bansal, M. Rizvi, V. Huard, P. Garg, C. Arnaud, R. Delater, STMicroelectronics
C. Roma, A. Ripp, MunEDA

IRPS 2014, May 2014, Hawaii, USA
Mar
31st
2014
Atmel-MunEDA Efficient Regression for Robustness Verification with WiCkeD
S. Kern, Atmel Automotive
M. Yakupov, G. Strube, MunEDA

DASS 2014, March 2014, Dresden, Germany
Feb
28th
2014
ZMDI-MunEDA Robustness Verification - Sign-off Regression Flow - DATE 2014
S. Getzlaff, ZMDI
G. Strube, MunEDA

DATE 2014, February 2014, Dresden, Germany
Dec
31st
2012
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) in 65nm
Zia Abbas, Mauro Olivieri, Marat Yakupov, Andreas Ripp
Elsevier Journal of Microelectronics, December 2012, Rome, Italy