Overview
Many thanks for your interest in the MUGM MunEDA Users Group Meeting 2023 that has taken place on May 16th & 17th (Tue/Wed), 2023 in Munich, Germany. The goal of the event was an intensive exchange of knowledge by new and experienced industrial users. MUGM provides an open forum for engineers interested in MunEDA solutions for Custom IC Circuit Design Migration, Analysis & Verification, Sizing & Optimization, High-Sigma Verification. Registration is now open!
Date:
May 16 – 10:00 a.m. to 04:00 p.m.
May 17 – 09:00 a.m. to 05:30 p.m.
Location:
Le Méridien
Bayerstraße 41
80335 Munich, Germany
The main focus of the MunEDA User Group Meeting 2023 has been on:
Circuit & IP Migration, Verification, Optimization & High-Sigma
The event has shown contributions from leading semiconductor companies, fabless design houses, foundries, research institutes and universities on the following topics:
- Efficient Analog Circuit migration with MunEDA SPT Schematic Porting tool in bulk CMOS, FinFET and FD-SOI technologies
- Linking MunEDA WiCkeD Optimizers with Intelligent IP Layout Generators for Fast Analog IC Design and IP Reuse
- Efficient and accurate SRAM hierarchical read path verification with iterative high-sigma analysis
- Area optimization of analog circuits
- Corner Verification and Performance Optimization of Ultra Low Power circuits in advanced node technologies
- Low-Voltage Analyses of Standard Cells in 22FDX Technology
- Efficient statistical characterization of standard cells with worst-case analysis and ML
- Integrating Analog Schematic Circuit Migration into an industrial design flow
- Learning from the implicit functional hierarchy in an analog netlist
- Circuit migration & optimization of sigma-delta converters with corner analysis and mismatch in 55nm
- Cooperative ML machine learning for design of electronic circuits and systems using robust simulation methods
- Design Optimization of Voltage Controlled Ring Oscillators (VCRO)
- EDA für ONoCs (Optical Networks on Chip)
- New WiCkeD feature Cellset for topology change during optimization of RF circuits
- High-Sigma Verification for SRAM and Standard Cell in leading edge technologies
- EDA Ideas & Research Lab Germany – Potential and Strategies for worldwide Exploitation
- MunEDA EDA tool demos and application tutorials, updates and roadmap
- And more
MUGM is an onsite in-person event in Munich, Germany. If you are interested in single presentations please contact us directly by email with info@muneda.com.
We have been very pleased to had you withour MunEDA User Group Meeting 2023 in Munich.
MUGM 2023 Group Picture
Program
Tuesday, 16th May, 2023
| 09:00 – 10:00 | Registration & Welcome Coffee |
| 10:00 – 11:00 | Session 1: Welcome Opening & What’s new |
| 10:00 – 10:20 | MunEDA – Welcome & Whats new A. Ripp, VP Sales & Marketing, MunEDA |
| 10:20 – 10:40 | MunEDA – Tutorial DSPF Post-layout Circuit Sizing Automation M. Pronath, MunEDA |
| 10:40 – 11:00 | MunEDA – Overview about Research Cooperation Projects INNOSTAR, BEYOND5, AnastASICA, MARIA, HoloDEC M. Dietrich, Dikuli |
| 11:00 – 11:20 | Coffee Break |
| 11:20 – 12:40 | Session 2: Optimization, FD-SOI, ONoCs |
| 11:20 – 11:45 | MunEDA – What’s new in WiCkeD 8.0 – Integration & R&D Roadmap F. Schenkel, VP Research & Development, MunEDA |
| 11:45 – 12:10 | STMicroelectronics (France, Grenoble) – WiCkeD Analog Circuit Migration and Optimization Benchmark Results C. Vaganay, STMicroelectronics |
| 12:10 – 12:40 | Technical University of Munich (TUM) – EDA for Optical Networks on Chip (ONoCs) U. Schlichtmann (Chair of Electronic Design Automation), Technical University of Munich |
| 12:40 – 14:00 | MUGM 2023 Group Picture & Lunch Break |
| 14:00 – 15:20 | Session 3: High-Sigma Verification & Yield Optimization |
| 14:00 – 14:20 | MunEDA Tool-Demo New WiCkeD Release Single GUI 8.03 C. Roma, MunEDA |
| 14:20 – 14:40 | STMicroelectronics (Italy, Catania) – Verification & Optimization of high sigma robust Read-Path for Non Volatile Memories (NVM) P. Coppa, STMicroelectronics |
| 14:40 – 15:00 | RacyICs (Dresden) – Using WiCkeD for Low-Voltage Analyses of Standard Cells in Globalfoundries 22FDX Technology D. Walter, RacyICs |
| 15:00 – 15:20 | Infineon Technologies – Determination of SRAM minimum operating voltage by using back-annotated worst-case core-cell and periphery circuits in transient simulations for read, write and access disturb operations P. Huber, Infineon |
| 15:20 – 15:40 | DWF Funds / Monopteros – EDA Ideas & Research Lab Germany – Potential and Strategies for worldwide Exploitation D. Friebel, DWF Funds / Monopteros |
| 15:40 – 16:00 | Coffee Break |
| 16:00 – 18:00 | Session 4: Circuit Migration, Process Porting & Retargeting |
| 16:00 – 16:25 | MunEDA Tool-Demo SPT Schematic Porting Tool M. Sylvester, MunEDA |
| 16:25 – 16:50 | STMicroelectronics (France, Grenoble) – Circuit Migration with SPT in 40nm Designflow M. Blattes, STMicroelectronics |
| 16:50 – 17:15 | Infineon Technologies – PD-Gen: A novel Object-Oriented Procedural Physical Design (OO-PPD) tool for Analog P&R / SPT Circuit Migration in Infineon H. Habal, Infineon Technologies |
| 17:15 – 17:35 | STMicroelectronics (Italy, Milan) – MunEDA integration in ST BCD Designflow E. Raciti, STMicroelectronics |
| 17:35 – 17:55 | Fraunhofer ENAS ASE (Paderborn) – Cooperative ML machine learning for design of electronic circuits and systems using robust simulation methods (KI4KMU MARIA) C. Hedayat, Fraunhofer ENAS ASE |
| 17:55 – 18:00 | MunEDA – Wrap-up MUGM 2023 and Preparation for Social Event A. Ripp, MunEDA |
| From 19:00 | Social Event at Augustiner Klosterwirt |
Wednesday, 17th May, 2023
| 08:30 – 09:00 | Registration & Welcome Coffee |
| 09:00 – 10:30 | Session 5: Analog Generators & Intelligent IP |
| 09:00 – 09:25 | Technical University of Munich (TUM) – Learning from the Implicit Functional Hierarchy in an Analog Netlist (HoloDEC) H. Gräb, Technical University of Munich |
| 09:25 – 09:50 | MunEDA Tutorial – WiCkeD Gangway (INNOSTAR) V. Glöckel, MunEDA |
| 09:50 – 10:15 | Fraunhofer IIA EAS (Dresden) – Linking WiCkeD and Intelligent IP Layout Generators for Fast Analog IC Design and IP Reuse (AnastASICA) B. Prautsch, Fraunhofer IIA EAS |
| 10:15 – 10:40 | Infineon Technologies (Italy) – Using WiCkeD Gangway in Infineon Analog Generator Projects D. Demiri, Infineon Technologies |
| 10:40 – 11:00 | Coffee Break |
| 11:00 – 12:30 | Session 6: LVF & PVT & mmWave |
| 11:00 – 11:20 | Reutlingen University – Research and Education in the Electronics & Drives Lab – Procedural Automation Solutions for Analog IC Design (HoloDeC) J. Scheible, Reutlingen University |
| 11:20 – 11:50 | Infineon Technologies – Standard Cell Characterization with LVF Liberty Variation Format and High-Sigma Methods for ULP Ultra Low Power K. Narayanan, Infineon Technologies |
| 11:50 – 12:10 | IMST (Kamp-Lintfort) – Hierarchical design of reusable IPs for integrated Radio Modules using embedded MunEDA Design Migration & IP Porting Flow (AnastASICA, INNOSTAR, HoloDEC) R. Wittmann, IMST |
| 12:10 – 12:30 | MunEDA Tutorial – LVF Standard Cell Characterization Flow with WiCkeD V. Glöckel, MunEDA |
| 12:30 – 14:00 | Lunch Break |
| 14:00 – 15:30 | Session 7: Machine Learning in Circuit Optimization |
| 14:00 – 14:20 | Fraunhofer ENAS ASE – Innovative Systems and Automated Design for 5G/6G Connectivity and Radar Applications (INNOSTAR) J. Temme, Fraunhofer ENAS ASE |
| 14:20 – 14:40 | STMicroelectronics (France, Marseille) – Methodology for Trimmed Circuits Sizing and PVT Optimization O. Lauzier, STMicroelectronics |
| 14:40 – 15:00 | SONIX Technology (Taiwan) – Circuit Verification and Cost (Area) Optimization using MunEDA WiCkeD H. J. Chen, SONIX Technology |
| 15:00 – 15:20 | FACTI Centro de Tecnologia da Informação Renato Archer (Brazil) – Optimization of the control circuit of an LCL Rad Hard using the WiCkeD EDA tool (CITAR Project) R. Hassib, CTI Renato Archer |
| 15:20 – 16:00 | Coffee Break |
| 16:00 – 17:00 | Session 8: Worldwide Projects for MunEDA |
| 16:00 – 16:20 | MunEDA – New WiCkeD feature Cellset for topology change during optimization of RF circuits (BEYOND5) M. Sylvester, MunEDA |
| 16:20 – 16:40 | NCS Nippon Control Systems (Japan) – Japan Semiconductor Industry Review K. Tsutsumi, NCS Nippon Control Systems |
| 16:40 – 17:00 | FACTI Centro de Tecnologia da Informação Renato Archer (Brazil) – Semiconductor & EDA in Brazil – The CITAR Project – Radiation Hardness by Design RHBD S. Finco, CTI Renato Archer |
| From 17:00 | MunEDA – Wrap-up MUGM 2023 and Farewell A. Ripp, VP Sales & Marketing, MunEDA |
Social Event
Augustiner Klosterwirt
Proceedings
Here you will find the password protected MUGM 2023 proceedings:
https://www.muneda.com/mugm/mugm-2023/proceedings/