MunEDA User Group Meetings

MUGM MunEDA User Group Meeting 2010, Oct 21st / Oct 22nd - Presentations

Infineon - IP & Re-Use - the next wave of a successful model

Synopsys - Synopsys Custom and Analog Mixed-Signal Overview & MunEDA WiCkeD Integration

STMicroelectronics - Advanced WiCkeD usage - A methodology for process variations impact analysis on huge circuits taking advantages of Synopsys CustomSim XA

X-Fab - Process Capabilities and Design Ecosystem of X-FAB Semiconductor Foundries

University Dresden - Exploration of Feasible Voltage Ranges in Analog CMOS Circuits Using Linearized-Operating-Point Transistor Models

MunEDA - Info about Survey, Expert's Tools & Demo Session (MUGM 2010)

Anvo-Systems - WiCkeD for nvSRAM Multi Corner Optimization (MUGM 2010)

Infineon - A new method for calculating standard deviations and correlation coefficients in modeling

LSI-TEC - Performance & Yield Optimization of a Switched DC/DC Converter in X-FAB XH035 Technology

STMicroelectronics - Embedded Flash memory Vx Linear Regulator porting from 90nm to 55nm technology while improving regulation accuracy to solve yield weakness

SK Hynix - Voltage Generator Fail Analysis & Issue Clear with f-DFM

MunEDA 2010 - MunEDA Tools and R&D-Roadmap 2010 (MUGM 2010)

Fraunhofer - Integration of Design Optimization into Automatic IP Generation with 1Stone and WiCkeD

STMicroelectronics - Multi-Testbench Analysis and Optimization of an LNA for AM radio receiver in 65 nm CMOS technology with WiCkeD 6.3

Infineon - Design Technology Interface & Sign-Off

Atmel - Design for Yield of High Sensitive Divider Circuits in SMARTIS technology

STARC - WiCkeD in STARCAD-AMS Design Flow

Altera - Applications of WiCkeD in FPGA Cell Design (MUGM 2010)

ON Semiconductor - Methodologies for Matching Analysis for Industrial Applications with WiCkeD

SK Hynix - Strategy for reducing the optimization time with the best performance

University Frankfurt - Design Centering for Automated Topology Synthesis of Analog Circuits

STMicroelectronics - Extraction Methods of VHDL/VerilogA Models for Analog Blocks, Usable Inside Time Domain Simulations