Analog Circuit Verification Methodology
Abstract:
MunEDA’s software package WiCkeD™ is a tool suite for circuit analysis, sizing, and modeling at transistor level.
Papers & Publications
Analog Circuit Migration and Optimization from 28nm Bulk to 14nm FinFET Technology: A Case Study (SPT, WiCkeD)
Abstract:
Advanced process nodes utilize FinFET devices, for their improved performance and leakage power characteristics.
High sigma parametric yield estimation for SRAM and standard cells
Abstract:
Verification of SRAMand standard cells poses a specific challenge to the designer because the parametric yield estimation is to be estimated for very low failure rates below 1ppb (10 –9), equivalent to >6 sigma robustness.
Fast Monte Carlo Methods for Custom Circuit Analysis in MunEDA WiCkeD
Abstract:
Verification of custom circuit designs in sub-100nm technologies poses a specific challenge to the designer because simulation runtime can be long.
Innovative Design Methodology for Analog-to-Digital and Digital-to-Analog Converters
Abstract:
ADCs and DACs are vital in modern signal processing, connecting analog and digital domains. Growing demands make manual design a bottleneck; MeKoWA project aims to automate ADC and DAC design.
A Multi-level Analog IC Design Flow for Fast Performance Estimation Using Template-based Layout Generators and Structural Models
Authors:
B. Prautsch, T. Markwirth, R. Wittmann; F. Schenkel, U. Eichler, J. Liebig
Innovative Design Methodology for Analog-to-Digital and Digital-to-Analog Converters
Authors:
R. Wittmann; F. Henkel, A. Ripp, A, Meyer, R. Wunderlich, S. Heinen, M. Dietrich
AnastASICA – Towards Structured and Automated Analog/Mixed-Signal IC Design for Automotive Electronics
Authors:
B. Prautsch, H. Dornelas, R. Wittmann; F. Henkel, F. Schenkel, J. Koelsch, C. Grimm, G. Strube
Analysis and optimization of voltage reference circuits based on sub-1V MOSFETs operating in different CMOS technologies
Authors:
G. Quarata, M. Pronath
BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization
Authors:
F. Cacho, A. Cros, Y. Federspiel, V. Huard (STMicroelectronics), C. Roma (MunEDA)
Optimal NBTI Degradation and PVT Variation Resistant Device Sizing in a Full Adder Cell
Authors:
Z. Abbas, M. Olivieri, G. Strube, A. Ripp
New Technology Migration Methodology for Analog IC Design (using MunEDA SPT Schematic Porting Tool)
Authors:
H. Dornelas, A. Schmidt, E. Fabris, G. Strube
Self-biased CMOS current reference based on the ZTC operation condition (using WiCkeD)
Authors:
P Toledo, D. Cordova, E. Fabris, H. Klimach, S. Bampi
I/O Design Optimization Flow for Reliability in Advanced CMOS Nodes with WiCkeD
Authors:
F. Cacho, A. Gupta, A. Aggarwal, G. Madan, N. Bansal, M. Rizvi, V. Huard, P. Garg, C. Arnaud, R. Delater, C. Roma, A. Ripp, MunEDA
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) in 65nm
Authors:
Z. Abbas, M. Olivieri, M. Yakupov, A. Ripp