A Multi-level Analog IC Design Flow for Fast Performance Estimation Using Template-based Layout Generators and Structural Models
Authors:
B. Prautsch, T. Markwirth, R. Wittmann; F. Schenkel, U. Eichler, J. Liebig
IEEE
BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization
Authors:
F. Cacho, A. Cros, Y. Federspiel, V. Huard (STMicroelectronics), C. Roma (MunEDA)
Optimal NBTI Degradation and PVT Variation Resistant Device Sizing in a Full Adder Cell
Authors:
Z. Abbas, M. Olivieri, G. Strube, A. Ripp
Self-biased CMOS current reference based on the ZTC operation condition (using WiCkeD)
Authors:
P Toledo, D. Cordova, E. Fabris, H. Klimach, S. Bampi
I/O Design Optimization Flow for Reliability in Advanced CMOS Nodes with WiCkeD
Authors:
F. Cacho, A. Gupta, A. Aggarwal, G. Madan, N. Bansal, M. Rizvi, V. Huard, P. Garg, C. Arnaud, R. Delater, C. Roma, A. Ripp, MunEDA
Yield optimization for low power current controlled current conveyor
Authors:
Z. Abbas, M. Olivieri, A. Ripp, G. Strube, M. Yakupov
Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
Authors:
V. Boos, J. Nowak, S. Henker, S. Hoeppner, M. Sylvester, H. Grimm
Robust Analog Design for Automotive Applications by Design Centering With Safe Operating Areas
Authors:
U. Sobe, K.-H. Rooch, D. Mörtl, A. Graupner, A. Ripp, M. Pronath, MunEDA GmbH, Munich, Germany
Experimental Verification of Simulation Based Yield Optimization for Power-On Reset Cells
Authors:
G. Rappitsch, O. Eisenberger, B. Obermeier, A. Ripp, M. Pronath
Initial sizing of analog integrated circuits by centering within topology-given implicit specifications
Authors:
G. Stehr, M. Pronath, F. Schenkel, H. Graeb, K. Antreich
WiCkeD: analog circuit synthesis incorporating mismatch
Authors:
K. Antreich, J. Eckmueller, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker, S. Zizala