Applications - High Sigma for Memory Design
WiCkeD High Sigma Analysis and Optimization - Highlights
- Fast, efficient, cost effective
- Robust & Standard Yield Estimation
- High-Sigma Yield & Robustness Estimation
- Sampling-based and Deterministic Yield Analysis Methods
- Saves on unnecessary silicon runs
Circuit Application examples
- Memory (SRAM, DRAM, CRAM, Flash, Embedded, FPGA, etc.) - Sense Amplifier, Bit Cells, Memory Interfaces
- Standard Cells, Flip Flop, Multibit Register, Look-up Tables
- Comparator, ADC, Transceiver, Bandgap, Charge Pump
- PLL, VCO, Oscillator, Filter, OpAmp, SerDes
- ... and many more
Challenges for high-sigma circuits and designs
Yield estimation, optimization and verification for high-yielding circuits such as SRAM or CRAM requiring high-sigma robustness is very challenging compared to other circuits:
- Such cells often appear by thousands or even millions on one chip
- The failure of any individual cell can result in the failure of the entire systems or chip, if no redundancy is implemented
For these cells it is critical to design cells with extremely low failure probability.
Typically a yield estimation method must be able to predict yield higher than 0.9999 -> at the tail of the distribution (>6σ for a Gaussian distribution) especially if some circuit performances (e.g. write time) show non-Gaussian distributions with long tails.
High-Sigma Estimation in WiCkeD - Monte Carlo Analysis
MunEDA WiCkeD includes several Monte Carlo Methods like:
- Direct Monte Carlo (DMC)
- Quasi-Monte Carlo (QMC)
- Important Sampling (IS)
Monte Carlo is seen as established and very robust yield estimation method, nevertheless all Monte Carlo Methods are limited and can not handle efficiently ultra high-sigma (>6σ) robustness analysis and not even circuit optimization tasks. Like also described in the figures below the verification of a yield Y > Ymin with 95% confidence for counting Method DMC is because of the huge required simulation number not feasible or realistic.

High-Sigma Estimation in WiCkeD - Worst Case Analysis
The Worst Case Analysis methods in WiCkeD are based on the calculation of the Worst-Case Point (WCP) and the so-called Worst-Case-Distance (WCD). This is the point on the specification boundary closest to the mean value. In WiCkeD WCP/WCD are calculated for every parameter simultaneously to verify consistent designs.
WiCkeD Worst-Case Analysis (WCA):
- Finds the combination of process parameter values that is most likely to violate the spec -> base for Yield Analysis
- WCA is efficient and can handle non-Gaussian specs with long tails
- The effort grows only linearly with the number of process parameters
- Can handle >6 sigma and higher robustness measures easily
- Needs much fewer samples compared to Monte Carlo Methods
- WCA/WCD results can be used efficiently for Robustness & Yield Optimization

High-Sigma Estimation in WiCkeD - Sensitivity Analysis
With WiCkeD BAS Sensitivity Analysis Designers can do sensitivity calculation (e.g. geometries, process, operating conditions, mismatch) and sweeps for all kinds of analyses (DC, AC, Tran, RF, ...) using all kind of industrial SPICE/FastSPICE simulators. The sweeps include constraint violation markers to verify designs will not be violated.
High-Sigma Estimation in WiCkeD - Mismatch Analysis
The WiCkeD deterministic mismatch analysis MMA identifies and analyses mismatch-relevant transistor pairs on selected circuit performances. The variance of these local variations will be analyzed based on dependencies of device pair geometries.

MunEDA WiCkeD - Technology Support
- WiCkeD is integrated and supports the major design frameworks and simulators as well as stand-alone or customized environments
- MunEDA WiCkeD supports many different foundry technologies and PDKs in many different technology nodes
- For more information and support contact www.muneda.com/contacts.php
Customer References
- MunEDA - Analyzing the Effects of Process Variation and Mismatch on Circuit Design: Monte Carlo and Alternatives (Part 1)
M. Pronath - MunEDA - Analyzing the Effects of Process Variation and Mismatch on Circuit Design: Monte Carlo and Alternatives (Part 2)
M. Pronath - SK Hynix - Analysis Method for The Parasitic RC Variation Problem by WiCkeD)
S. Lee - STMicroelectronics - Worst Case Analysis and Yield Optimization of a micro-power precision OpAmp based on an advanced Offset Cancellation Chopper technique in HF7CMOS (350nm) from APM-IMS with WiCkeD
A. Ciccazzo
Applications - Low Power Tuning & Sizing for Custom Circuits
MunEDA Low Power Custom IC Design (Analog, RF) - Highlights
- Automated Circuit Performance Tuning
- Design for Yield & High-Sigma Robustness
- Robustness Verification
Challenges for Low Power Custom IC Design
In all designs today, power is a concern. For mobile devices, very low power consumption is a main design objective. Especially analog and mixed-signal designers in the fields of:

spend much effort to create circuits that fulfill their specification reliably with a small power budget. Within such circuits designers have to consider many influence factors such as:

Within the circuit sizing process in regards to low and ultra-low power design all these influence factors and their trade-offs have to be taken into account.
Typical Circuit Applications - Full Custom Low Power Design
Typical applications for using WiCkeD in full custom low power design are:

Low Power Custom IC Design Flow with MunEDA WiCkeD
The MunEDA WiCkeD tool set provides significant productivity gains over traditional design methods, and enables advanced circuit architectures with lower power consumption and higher performance.
High performance, high speed, low power design, low noise requirements happen pre-dominantly in advanced technology nodes. For this reason designers can benefit from MunEDA's circuit sizing tools to optimize performances, power, noise, area, yield and others.
WiCkeD has sufficient capacity to analyze and size large circuits:
MunEDA world- class outstanding circuit optimization tools help designers to save a significant amount of time on circuit sizing and optimization for speed and power consumption.

When having a circuit testcase with a power or noise issue the designer can use the MunEDA WiCkeD tools to analyse design challenges and fix it using the powerful MunEDA optimizers. First step for performance tuning is always a feasibility check if all design constraints are fulfilled. Next a sensitivity and trade-off analysis will be fulfilled to check the circuit performances. A deterministic nominal optimization will be used to bring all performances into their nominal specification bounds. As next the statistical effects such as behavior at process and operating corners will be checked for the given design and a statistical mismatch analysis will be fulfilled. Finally the circuit will be optimized for best robustness and yield with YOP Yield Optimization. All results will be verified using MunEDA WiCkeD high-performance Worst-Case and High-Sigma Analysis methods including statistical verification with WiCkeD’s advanced Monte Carlo Analysis. Result is a circuit testcase optimized for low-power and low-noise with best possible performance.
WiCkeD has sufficient capacity to analyze and size large circuits:
- >100 specifications and constraints handled simultaneously
- >200 design variables, >2000 MOS
- Post-layout effects and parasitics supported
- Multiple test benches, goals, corners, considered
Solution - WiCkeD Tool Flow for Low-Power Design
MunEDA world- class outstanding circuit optimization tools help designers to save a significant amount of time on circuit sizing and optimization for speed and power consumption.

When having a circuit testcase with a power or noise issue the designer can use the MunEDA WiCkeD tools to analyse design challenges and fix it using the powerful MunEDA optimizers. First step for performance tuning is always a feasibility check if all design constraints are fulfilled. Next a sensitivity and trade-off analysis will be fulfilled to check the circuit performances. A deterministic nominal optimization will be used to bring all performances into their nominal specification bounds. As next the statistical effects such as behavior at process and operating corners will be checked for the given design and a statistical mismatch analysis will be fulfilled. Finally the circuit will be optimized for best robustness and yield with YOP Yield Optimization. All results will be verified using MunEDA WiCkeD high-performance Worst-Case and High-Sigma Analysis methods including statistical verification with WiCkeD’s advanced Monte Carlo Analysis. Result is a circuit testcase optimized for low-power and low-noise with best possible performance.
MunEDA WiCkeD - Technology Support
- WiCkeD is integrated and supports the major design frameworks and simulators as well as stand-alone or customized environments
- MunEDA WiCkeD supports many different foundry technologies and PDKs in many different technology nodes
- For more information and support contact www.muneda.com/contacts.php
Customer References
- MunEDA - Low Power OpAmp Optimization with WiCkeD
M. Siu - Altera - Power and performance optimization with transistor variables on custom circuits using MunEDA WiCkeD
G. H. Oh - STMicroelectronics - Application of MunEDA WiCkeD - Agilent GoldenGate integration for corner analysis and sizing of RF circuits
A. Ciccazzo - CEITEC - RFID, Wireless Communications and Digital Multimedia Technology made in Brasil
F. Chavez - University Erlangen - Verification and Optimization of Digital Radio Receiver Sub Circuits (LFoundry 150nm)
C. Schmidt - IMMS - Using WiCkeD in MEMS design
V. Boos - University Dresden - Low Power MPSoC Circuit Design in GLOBALFOUNDRIES 28nm CMOS with WiCkeD
S. Höppner - STMicroelectronics - Reducing Mismatch Impact by means of Proper Biasing in Fully Differential, Low Power CMOS Structures
A. Capasso, A. Colaci - ON Semiconductor - Methodologies for Mismatch Sizing and Corner Verification for Automotive Applications with WiCkeD
J. Daniels
Applications - Standard Cell & I/O Custom Cell Design Sizing
WiCkeD for Standard & I/O Cell Design - User Benefits
- Smart, Fast, Reliable!
- Quickly detect critical transistors and non linearities vs. operating conditions
- Determine Performance Worst Case Operating Conditions for each corner
- Optimize Performance @ Nominal + Worst Case Operating Conditions & Corners!
Standard Cells
Standard cells are group of transistors and interconnect structures that provide boolean logic funtions (e.g. AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). The simplest cells are direct representations of the elemental NAND, NOR, and XOR boolean function, although cells of much greater complexity are commonly used (such as a 2-bit full-adder, or muxed D-input flipflop).
Standard Cell Design Objectives & Challenges
The major objectives for the design of standard cells are:
-
Optimization of standard cell main performances
- Improve Timing, Save Power
-
Analysis & Optimization of standard cell performances robustness
- Ensure immunity to process parameter variations (global & local variation, mismatch)
- Statistical Analysis
-
Achieve reliable solutions for desired implementations
- Sustaining electrical constraints (multi voltage operating points, frequencies)
- Matching layout requirements (Area, DFM)
Solution - MunEDA WiCkeD Analysis and Optimization for Standard Cell Design & Reliability Flow

MunEDA WiCkeD Analysis and Optimization for Standard Cell Design Flow
Using different analysis and optimization tools of MunEDA WiCkeD the standard cell designer can solve many of the above described challenges. He first starts with the selection and description of the testcase including testbenches (e.g. Flip Flop, Latch, o.a.). Main circuit features are given by the circuit topology, technology and performance definitions. Using the powerful WiCkeD CED Constraint Editor the designer can add all desired netlists with one mouse-click, then define the constraints and performances and also check the initial conditions and corners. The user can with WiCkeD CRN Corner Run Analysis perform a corner run for every constraint. After this using WiCkeD BAS Basic & Sensitivity Analysis the designer identifies critical transistors and checks non-linearities vs the defined operating parameters. With WiCkeD WCO Worst Case Operation analysis the designer then can cross-check easily the worst case performances against all operating conditions and corners.
After this he can use the powerful and numerous silicon-proven optimization algorithms of WiCkeD DNO Deterministic Optimization to determine the performance worst case operating conditions for each corner and finally run performance optimization @ nominal + worst case operating conditions and corners. Goal is to converge all performances with a minimum number of iterations including the fulfilment of all constraints to guarantee a feasible solution


With MunEDA WiCkeD the standard cell designer can very easily setup his circuit for statistics and perform mismatch and yield analysis. For this reason he only has to use WiCkeD CED Constraint Editor of the already setup cell to set mismatch parameters, activate the mismatch devices and match physical identical transistors. For more in-depth statistical analyses numerous powerful high-sigma analysis methods are available such as Corner Run Analysis, Monte-Carlo-Analysis, Process Sensitivity Analysis, Parameter Distribution, Performance Distribution, Parameter Sweeps, Worst-Case Analysis & Diagnosis, Mismatch Analysis, and many more. WiCkeD’s unique and powerful silicon-proven YOP Yield Optimization improves yield and performance reliability to the maximum.


MunEDA WiCkeD for Standard Cell Reliability Flow

With MunEDA WiCkeD the standard cell designer can very easily setup his circuit for statistics and perform mismatch and yield analysis. For this reason he only has to use WiCkeD CED Constraint Editor of the already setup cell to set mismatch parameters, activate the mismatch devices and match physical identical transistors. For more in-depth statistical analyses numerous powerful high-sigma analysis methods are available such as Corner Run Analysis, Monte-Carlo-Analysis, Process Sensitivity Analysis, Parameter Distribution, Performance Distribution, Parameter Sweeps, Worst-Case Analysis & Diagnosis, Mismatch Analysis, and many more. WiCkeD’s unique and powerful silicon-proven YOP Yield Optimization improves yield and performance reliability to the maximum.

MunEDA WiCkeD - Technology Support
- WiCkeD is integrated and supports the major design frameworks and simulators as well as stand-alone or customized environments
- MunEDA WiCkeD supports many different foundry technologies and PDKs in many different technology nodes
- For more information and support contact www.muneda.com/contacts.php
Customer References
- MunEDA - Automated Numerical Resizing of Standard Cells in WiCkeD
P. Tavares - STMicroelectronics - Overview of WiCkeD capabilities for Standard Cell Performances Optimization & High Sigma Yield Analysis
N. Ben Salem - University Frankfurt - An Unattended Circuit Optimization Flow for Digital Standard Cells using WiCkeD
M. Meissner - STMicroelectronics - Sizing of standard cells in worst-case process conditions in 110nm BCD9s
F. Adduci
Applications - RSM Circuit Modelling & Model Generation
Circuit Modelling & Model Generation with WiCkeD RSM
User Benefits:
- Increased circuit design flexibility
- Speed-up of simulations and reducing simulation effort
- Mixed transistor-system-level circuit optimization possible
- Provides more Flexibility to the designer
Often individual custom circuits will be embedded into larger systems and whole chips and therefore require consistency in circuit and system-level simulation.
For this reason such circuits should be modelled easily to check the circuit behaviour and performances and even statistical influences on the circuits and the whole system. For this reason MunEDA offers its tool RSM (Response Surface Modelling) as part of the WiCkeD tool suite.
Features of WiCkeD RSM:
- Creates response surface models of circuit performances with respect to parameters
- Numerous Modeling Types: Latin Hypercube, Polynomial, RBI Radial Basis Functions, ARBI, PolyRBI, Cubic RBI, a.o.
- Models can be used inside WiCkeD with other analyses and optimization modules
- Models can be written in Verilog or VHDL format
- Operating conditions can be considered
Customer References
- Atmel - Design for Yield of High Sensitive Divider Circuits in SMARTIS technology
W. Schneider, S. Kern, M. Lampp - STMicroelectronics - Extraction Methods of VHDL/VerilogA Models for Analog Blocks, Usable Inside Time Domain Simulations
A. Martino, M. Micciche, A. Conte - STMicroelectronics - Surrogate models for the analog circuit simulation based on a machine learning approach (ManOn)
A. Ciccazzo, C. Vicari, V. Latorre, S. Ludici
Applications - Model Characterization & Process Model Backward Propagation
Process Model Characterization & Process Model Backward Propagation with MunEDA WiCkeD
User Benefits:
- Check correlation between corner models with Monte Carlo distribution
- Useful for both design & production engineers

For Monte Carlo simulation statistical model parameters are needed:
- Local parameter variations for device mismatch
- Global parameter variations for process variations
- Correlation parameters for the dependency between global parameters.
In many cases it is hard to calculate standard deviations and correlation coefficients for global model parameter variations that are based on statistical measurements. From PCM measurements the standard deviations and correlation coefficients of PCM parameters (P) are well known, whereas for Monte Carlo simulation the standard deviations and correlation coefficients of model parameters (M) are needed.
With WiCkeD it is possible to set up a linear equation that describes the relations between the standard deviations and correlation coefficients of M and P and solve it in one step.


MunEDA WiCkeD - Technology Support
- WiCkeD is integrated and supports the major design frameworks and simulators as well as stand-alone or customized environments
- MunEDA WiCkeD supports many different foundry technologies and PDKs in many different technology nodes
- For more information and support contact www.muneda.com/contacts.php